A common prior art approach to demodulating PSK (phase-shift keyed) signals is to apply the received PSK signal to one input of a multiplier circuit comprising a part of a double balanced modulator and to supply a one data bit delayed version of the same PSK signal to the second input of the multiplier circuit. As is well-known to those skilled in the art, the output of a multiplier circuit includes not only the sum and difference versions of the input signals, but also components of the original frequency input signals and various harmonics. Although the multiplier in a PSK demodulator is multiplying two identical frequency signals merely having different phases, the PSK signals are comprised of a high frequency carrier whose phase is modulated by the data rate. The result is a plurality of signal frequencies which are a function of the carrier frequency and the data rate and these other frequency components must be compensated for in the detection circuitry.
As may be realized by those skilled in the art, limiters are often used in connection with FSK (frequency shift keyed) demodulators. Limiters are used both with FSK demodulators having a delay and sum type construction as well as multiplier-type construction. The limiters in FSK circuits do improve the performance.
Prior attempts to use limiters in connection with PSK signal demodulation have shown that a limiter prior to a multiplier-type demodulator not only does not improve the bit error rate performance but actually degrades the performance of the circuit. It has been widely assumed by those skilled in the art that a limiter would therefore not significantly improve the performance of the previously inferior delay and sum approach to demodulating PSK signals. However, the applicant has discovered that such assumptions were incorrect.
The present invention accomplishes the demodulating action by summing the PSK signal with a one bit delayed version of the signal to produce an output signal which, when the two inputs are in-phase, has a double amplitude and when the two inputs are out-of-phase, has a cancelation effect or minimal output value. Thus, envelope detecting this signal will provide a data stream which is representative of the original input data.
Prior art attempts to accomplish the demodulating action by summing the PSK signal with a one bit delayed version as presented above, have typically been abandoned in situations where the inevitable noise signals, which vectorially add to the carrier signal, produce a resultant signal whose phase and amplitude changes to such a large extent that decisions made on the detected signal are unacceptably unreliable. This results in an unacceptably high BER (bit error rate).
The present invention overcomes this limitation or problem of the delay and sum type demodulator by inserting a limiter immediately prior to the delay and summing means which limiter reduces the amplitude of the signal to an amplitude which is less than the typical fluctuation extremes of the carrier as a result of the added noise (vectorial modulation). This constant amplitude and limited signal contains a sufficiently low phase distortion so that typical level detectors can more reliably distinguish between the logic levels represented by the phase alterations and thus, provide an acceptable bit error rate from the amplitude detector.
If the data transmitted was differentially encoded before being phase-shift keyed, the detected signal is directly representative of the input data stream. However, if the data stream transmitted was used to directly phase modulate the carrier to produce a phase-shift keyed signal, the envelope detected signal must be further processed to reestablish the original data stream. A limiter, summing circuit and envelope detector combination is more cost efficient to produce than is a multiplier and its accompanying spurious signal compensating circuits for high bit rates.
It may be noted that prior art FSK demodulators (discriminators) of the delay and multiply-type, have used limiters to remove the amplitude fluctuations contributed by noise and have been beneficial in improving the bit error rate of these demodulators. However, prior attempts to use limiters on multiply-type PSK demodulators have proven to have no beneficial effect since the only time a multiply PSK demodulator produces errors is when there is a signal vector in the wrong direction.
In view of the lack of beneficial effects of limiters applied to multiply-type PSK demodulators and the completely different attributes of FSK and PSK signals, it has been assumed by those in the field prior to the present invention that limiters would provide no performance benefit in delay and add or delay and subtract type demodulator circuits.
It is therefore an object of the present invention to provide an improved phase-shift keyed demodulator circuit.